As it is well known, a micro-electro-mechanical system (MEMS) device is a microdevice that integrates mechanical and electrical functions in a silicon chip realized using lithographic microfabrication techniques.
The final assembled device or chip is typically composed of a MEMS die and optionally application-specific integrated circuits (ASICs) assembled on top of a substrate both in side by side or stacked configuration, using standard assembly processes.
In fact, it is well known that integrated circuits (IC) are fabricated on the surface of a semiconductor wafer and later singulated into individual semiconductor devices, which may be referred to as a “die” or “dice” herein. Since the material of a semiconductor wafer—commonly silicon—tends to be relatively fragile and brittle, dice are usually assembled into protective housings, or “packages,” before being interconnected with a printed circuit board (PCB), the package ensuring the interconnection between the dice and the board.
The semiconductor device is normally encapsulated within a protecting material (normally epoxy resin), or cap or other molding compound, to ensure electrical and mechanical protection, in general, as well as to protect against moisture, dust, and other external agents.
In the case where more than one die is required, the semiconductor devices (e.g. MEMS) can be found in a variety of relations with respect to each other, depending on the type of stacking configuration that applies. The devices can thus be found to be in the side by side, stacked, inversely stacked, or other conformation.
The LGA/BGA substrate is covered with patterns, or traces, of conductive material layers (usually copper), that are insulated from one another by alternating layers of insulating or dielectric material. Conductive traces are also separated within each layer by an insulating, or dielectric, material.
Conductive tunnels, called “vias”, typically pass through insulating layers according to a vertical orientation with respect to the layers, to form conductive pathways between adjacent conductive patterns, thus providing the electrical connection between the metal layers provided on the dice. Such vias are required in the package substrate of a die or a MEMS device to insure the correct signal transmission between different metal layers.
Commonly used in the field are land grid array (LGA) packages wherein one or more dice are mounted on a package substrate and enclosed in a homogenous material molding compound.
The LGA package is so named because the package substrate has an array of electrical contact pads, or “lands,” arranged in a grid pattern on its underside. The lands are coupled with the printed circuit board (PCB) generally with solder material. The PCB is substantially a support board for mounting the LGA/BGA packages.
LGA packages are highly desirable in those cases where size reduction, performance and cost issues are of particular concern.
The upper surface of the package substrate is surmounted by a silicon die, for example a MEMS device, which can be coupled to pads or to bond fingers on the top metal layer of the LGA by wire-bonding. Normally, the die is attached to the substrate with the aid of an adhesive material such as a glue or a tape.
It is thus clear that, as well as constituting the mechanical support of the die or MEMS device, the package substrate also has a fundamental role from the electrical point of view.
A standard package substrate is schematically shown in FIG. 1, globally indicated with 10.
The substrate 10 is made of a polymeric material (for example, bismaleimide and triazine (BT) resin) core 4 and comprises a pair of metal layers 3a, 3b consisting of a top metal layer 3a and a bottom metal layer 3b each consisting of a first sub-layer surrounding the core 4 (copper foil) and a second sub-layer (copper plating) overlying the first sub-layer. The pair of metal layers 3a, 3b is in turn surrounded by a top 1a and a bottom 1b solder mask layer.
The number of metal layers that can be used in the composition of package substrates 10 is variable and typically ranges between 2 and 4.
For a two-layer LGA/BGA substrate, standard thickness values are in the range of 200 to 300 μm, wherein the core is approximately 100 μm or 200 μm, each copper layer is 12-28 μm, and each solder mask layer is approximately 25 μm in thickness.
In the example shown in FIG. 1, vias 8 are realized by plated through holes, or PTH, drilled in the core 4 to provide electrical connections between the two copper layers 3a and 3b. Typical dimensions of drill are in the range of 100 to 200 μm in diameter.
Along the production line of, for example, a MEMS device, the assembly of the package can represent quite a critical step for such a sensitive electronic device. The package, in fact, can undergo considerable mechanical stress during manufacturing, especially during the molding step, which can lead to tilting of the die and failure by delamination of its cap, with consequent loss of the sealing effect, which in turn affects the durability of the device as well as its quality of performance, in terms of offset stability and drift of the package, upon use.
During the assembly steps, under considerable thermal stress conditions, the substrate strip where the dice are mounted on can undergo warpage, which results in high stress conditions for the mounted dice.
To overcome some of these problems, it is known to balance the superficial distribution of the patterned copper layers by inserting copper meshes.
Other known solutions comprise package substrates having an increased thickness in order to enhance their tolerance to the production processes usually employed in the field. In this case, however, the total thickness of the package is also increased, which is undesirable, for obvious reasons.
However, in the case of devices that are especially sensitive to the mechanical and thermal stresses of the assembly step, in particular the molding step, such as the MEMS devices, such known solutions are not always sufficient to insure effective balancing and mechanical stability, and an optimal final packaged device.
The problem underlying embodiments is thus that of providing a package substrate overcoming the above-mentioned limitations of the prior art, and which is thus capable of withstanding the mechanical and thermal stresses of the assembly process, in particular of the molding step, and a method of production thereof.